# ../../../test/prsim/cbit_test_stat-01.prsimrc
# @haco@ cbit_test_stat.haco-a
initialize
weak-rules on
set write 0
set _pchg 0
set din 0
set bl 1
set _bl 1
mode reset
unstable-dequeue
unstable warn
set wl[0] 0
set wl[1] 0
set wl[2] 0
set wl[3] 0
cycle
set p[0].t 0
set p[0].f 1
set p[1].t 0
set p[1].f 1
set p[2].t 0
set p[2].f 1
set p[3].t 0
set p[3].f 1
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 1
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[1] 1
cycle
assert p[1].t 0
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 0
assert _bl 1
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 1
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[1] 1
cycle
assert p[1].t 1
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 1
assert _bl 0
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 3
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[3] 1
cycle
assert p[3].t 0
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 0
assert _bl 1
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 2
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[2] 1
cycle
assert p[2].t 1
set wl[2] 0
cycle
set write 0
cycle
set wl[2] 1
cycle
assert bl 1
assert _bl 0
set wl[2] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 2
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[2] 1
cycle
assert p[2].t 1
set wl[2] 0
cycle
set write 0
cycle
set wl[2] 1
cycle
assert bl 1
assert _bl 0
set wl[2] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 3
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[3] 1
cycle
assert p[3].t 0
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 0
assert _bl 1
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 1
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[1] 1
cycle
assert p[1].t 1
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 1
assert _bl 0
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 1
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[1] 1
cycle
assert p[1].t 1
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 1
assert _bl 0
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 1
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[1] 1
cycle
assert p[1].t 0
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 0
assert _bl 1
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 1
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[1] 1
cycle
assert p[1].t 0
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 0
assert _bl 1
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 3
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[3] 1
cycle
assert p[3].t 1
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 1
assert _bl 0
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 1
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[1] 1
cycle
assert p[1].t 0
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 0
assert _bl 1
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 1
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[1] 1
cycle
assert p[1].t 0
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 0
assert _bl 1
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 3
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[3] 1
cycle
assert p[3].t 1
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 1
assert _bl 0
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 1
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[1] 1
cycle
assert p[1].t 0
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 0
assert _bl 1
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 2
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[2] 1
cycle
assert p[2].t 1
set wl[2] 0
cycle
set write 0
cycle
set wl[2] 1
cycle
assert bl 1
assert _bl 0
set wl[2] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 3
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[3] 1
cycle
assert p[3].t 0
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 0
assert _bl 1
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 3
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[3] 1
cycle
assert p[3].t 1
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 1
assert _bl 0
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 3
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[3] 1
cycle
assert p[3].t 0
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 0
assert _bl 1
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 2
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[2] 1
cycle
assert p[2].t 0
set wl[2] 0
cycle
set write 0
cycle
set wl[2] 1
cycle
assert bl 0
assert _bl 1
set wl[2] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 2
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[2] 1
cycle
assert p[2].t 1
set wl[2] 0
cycle
set write 0
cycle
set wl[2] 1
cycle
assert bl 1
assert _bl 0
set wl[2] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 2
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[2] 1
cycle
assert p[2].t 0
set wl[2] 0
cycle
set write 0
cycle
set wl[2] 1
cycle
assert bl 0
assert _bl 1
set wl[2] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 1
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[1] 1
cycle
assert p[1].t 0
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 0
assert _bl 1
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 1
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[1] 1
cycle
assert p[1].t 1
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 1
assert _bl 0
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 3
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[3] 1
cycle
assert p[3].t 1
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 1
assert _bl 0
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 3
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[3] 1
cycle
assert p[3].t 0
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 0
assert _bl 1
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 2
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[2] 1
cycle
assert p[2].t 0
set wl[2] 0
cycle
set write 0
cycle
set wl[2] 1
cycle
assert bl 0
assert _bl 1
set wl[2] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 2
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[2] 1
cycle
assert p[2].t 1
set wl[2] 0
cycle
set write 0
cycle
set wl[2] 1
cycle
assert bl 1
assert _bl 0
set wl[2] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 3
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[3] 1
cycle
assert p[3].t 0
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 0
assert _bl 1
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 3
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[3] 1
cycle
assert p[3].t 1
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 1
assert _bl 0
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 2
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[2] 1
cycle
assert p[2].t 1
set wl[2] 0
cycle
set write 0
cycle
set wl[2] 1
cycle
assert bl 1
assert _bl 0
set wl[2] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 1
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[1] 1
cycle
assert p[1].t 0
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 0
assert _bl 1
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 3
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[3] 1
cycle
assert p[3].t 0
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 0
assert _bl 1
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 3
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[3] 1
cycle
assert p[3].t 1
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 1
assert _bl 0
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 3
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[3] 1
cycle
assert p[3].t 0
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 0
assert _bl 1
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 1
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[1] 1
cycle
assert p[1].t 0
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 0
assert _bl 1
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 1
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[1] 1
cycle
assert p[1].t 1
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 1
assert _bl 0
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 3
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[3] 1
cycle
assert p[3].t 0
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 0
assert _bl 1
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 2
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[2] 1
cycle
assert p[2].t 1
set wl[2] 0
cycle
set write 0
cycle
set wl[2] 1
cycle
assert bl 1
assert _bl 0
set wl[2] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 2
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[2] 1
cycle
assert p[2].t 1
set wl[2] 0
cycle
set write 0
cycle
set wl[2] 1
cycle
assert bl 1
assert _bl 0
set wl[2] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 3
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[3] 1
cycle
assert p[3].t 0
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 0
assert _bl 1
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 1
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[1] 1
cycle
assert p[1].t 1
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 1
assert _bl 0
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 1
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[1] 1
cycle
assert p[1].t 1
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 1
assert _bl 0
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 1
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[1] 1
cycle
assert p[1].t 0
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 0
assert _bl 1
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 1
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[1] 1
cycle
assert p[1].t 0
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 0
assert _bl 1
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 3
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[3] 1
cycle
assert p[3].t 1
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 1
assert _bl 0
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 1
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[1] 1
cycle
assert p[1].t 0
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 0
assert _bl 1
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 1
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[1] 1
cycle
assert p[1].t 0
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 0
assert _bl 1
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 3
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[3] 1
cycle
assert p[3].t 1
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 1
assert _bl 0
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 1
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[1] 1
cycle
assert p[1].t 0
set wl[1] 0
cycle
set write 0
cycle
set wl[1] 1
cycle
assert bl 0
assert _bl 1
set wl[1] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 0
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[0] 1
cycle
assert p[0].t 0
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 0
assert _bl 1
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 2
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[2] 1
cycle
assert p[2].t 1
set wl[2] 0
cycle
set write 0
cycle
set wl[2] 1
cycle
assert bl 1
assert _bl 0
set wl[2] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 3
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[3] 1
cycle
assert p[3].t 0
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 0
assert _bl 1
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 0
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[0] 1
cycle
assert p[0].t 1
set wl[0] 0
cycle
set write 0
cycle
set wl[0] 1
cycle
assert bl 1
assert _bl 0
set wl[0] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 3
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[3] 1
cycle
assert p[3].t 1
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 1
assert _bl 0
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 3
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[3] 1
cycle
assert p[3].t 0
set wl[3] 0
cycle
set write 0
cycle
set wl[3] 1
cycle
assert bl 0
assert _bl 1
set wl[3] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 2
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[2] 1
cycle
assert p[2].t 0
set wl[2] 0
cycle
set write 0
cycle
set wl[2] 1
cycle
assert bl 0
assert _bl 1
set wl[2] 0
cycle
set _pchg 0
cycle
echo Writing 1 to addr 2
set _pchg 1
cycle
set din 1
cycle
set write 1
cycle
assert bl 1
assert _bl 0
set wl[2] 1
cycle
assert p[2].t 1
set wl[2] 0
cycle
set write 0
cycle
set wl[2] 1
cycle
assert bl 1
assert _bl 0
set wl[2] 0
cycle
set _pchg 0
cycle
echo Writing 0 to addr 2
set _pchg 1
cycle
set din 0
cycle
set write 1
cycle
assert bl 0
assert _bl 1
set wl[2] 1
cycle
assert p[2].t 0
set wl[2] 0
cycle
set write 0
cycle
set wl[2] 1
cycle
assert bl 0
assert _bl 1
set wl[2] 0
cycle
set _pchg 0
cycle
