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.sp |2c
\fBMagic Tutorial #S-3: Transistor stacks
.ds LH Magic Tutorial #S-3
.ds RH \*(DY
.ds CF - % -
.sp 1c
.NL
\fIRajit Manohar\fR
.sp 1c
Department of Computer Science
California Institute of Technology
Pasadena, CA 91125

.SM
This tutorial corresponds to Magic version 6.5-scm.


.DE
.SM
.LP
\fBTutorials to read first:\fR
.IP
#S-1
.br
.LP
\fBCommands introduced in this tutorial:\fR
.IP
stack.p, stack.n, stack.tallp, stack.talln, prs.draw, prs.mgn,
prs.talldraw, prs.tallmgn
.LP
\fBMacros introduced in this tutorial:\fR
.IP
none
.br
.NL
.sp 1c

.NH 1
Stacks
.PP
The first step in laying out a gate/operator using magic tends to
involve drawing the transistor stacks without any wiring, labelling
all the important nodes in the circuit. Since the extractor pretends
that nodes that have the same label are electrically connected, the
extracted circuit can be simulated using SPICE to obtain some
indication of the power/speed of the circuit.

\fBstack.tallp\fR and \fBstack.talln\fR can be used to draw such
transistor stacks and place contacts where required. These two
functions take a transistor width and a list of strings that represent
the stack as their arguments, and draw the stack vertically (gates run
horizontally) at the current box. For example,

.DS I
\fB(stack.tallp 40 '(("Vdd") "a" "b" ("Inode") "d" ("out")))
.DE

draws a vertical stack of p-transistors with the diffusion being 40
lambda wide. The stack begins with a contact labelled "Vdd", followed
by two gates labelled "a" and "b", followed by a contact labelled
"Inode", followed by a gate labelled "d", followed by a contact
labelled "out". Contacts are indicated by placing the string for the
label in parenthesis. Note the presence of the quote that prevents the
interpreter from attempting to evaluate the list.

The contact width and contact-gate spacing together amount to more
than the spacing between adjacent gates. Often it is desired to
eliminate this extra space by jogging the poly wires so that the
amount of internal diffusion capacitance is minimized. The functions
\fBstack.p\fR and \fBstack.n\fR can be used to do so. Typing

.DS I
\fB(stack.tallp 40 '(("Vdd") "a" "b" ("Inode") "d" ("out")))
.DE

will draw the same stack and jog the poly wires corresponding to the
gate for "d".


.NH 1
Production rules
.PP

The functions \fBprs.draw\fR and \fBprs.mgn\fR can be used to draw the
transistor stacks that implement a production rule. For instance,

.DS I
\fB(prs.draw 40 "x & y -> z-")
.DE

will draw the stack required to implement the specified production
rule with width 20. The function takes a gate width and a single
production rule as its arguments. Note that the production rules must
be in negation normal form, i.e., all negations must be on variables.

Contacts can be shared between operators by providing a list of
production rules as input to \fBprs.mgn\fR, as follows:

.DS I
\fB(prs.mgn 40 20 "x & y -> z-" "u & v -> w-" "~x & ~y -> z+")
.DE

The contact to GND will be shared between the pull-down stacks for z
and w.

Both production-rule drawing function ensure that the variable order
in the production rule (from left to right) corresponds to the gate
order in the transistor stacks (from power supply to output).

It is not always possible to directly draw a production rule in a
single stack with no additional internal contacts. In this case, the
function creates an internal node name of the form "_" followed by a
number. You can search for these using \fB(label.search "_*")\fR,
followed by \fB(label.find-next)\fR.  To complete the implementation,
you will have to wire up these internal contacts as well.

Both \fBprs.mgn\fR and \fBprs.draw\fR draw the transistor stacks using
\fBstack.p\fR and \fBstack.n\fR. The variants \fBprs.tallmgn\fR and
\fBprs.talldraw\fR use \fBstack.tallp\fR and \fBstack.talln\fR
instead.
