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Invited Talk 1. 9:15-10:15, Monday, March 14, 2005.
Deep Pipelines vs. Risk and Power Walls
Bob Colwell, R.E. Colwell and Assoc., Inc (formerly at Intel)
Intel's x86 processors pushed pipelining and clock rates until physics
stopped us. Less obviously, we were also pushing complexity, and therefore
risk. We now know where the limits to these trends lie: with the Prescott
processor. This talk will explore the nature of risk in chip developments,
how the ever-deepening pipelines in the Pentium series affected and were
affected by perceived risk and thermals, and where the future will take us.
Invited Talk 2. 9:00-10:00, Tuesday, March 15, 2005.
Proximity Communication and Time
Robert Drost and Ivan Sutherland, Sun Microsystems Laboratories
Two integrated circuit chips placed face-to-face can communicate
without direct electrical contact. The capacitive coupling between
their top-level metal layers can carry data. We have demonstrated such
"proximity communication" with data bits on 50 micron centers and data
rates similar to on-chip wires. Such communication offers attractive
speed, density, and energy economy, but requires accurate mechanical
alignment. Robert Drost will summarize our work.
Proximity communication requires sensitive amplifiers to compensate for
the attenuation suffered as signals pass from one chip to the other.
Sensitive sampling amplifiers, such as the "regenerative sense
amplifiers" found in a DRAM, distinguish between two binary states when
told to act. Such amplifiers are useful for receiving the data bits in
a bundled-data system in which the control signals tell them when to
act. However, they are inappropriate for control signals with
uncertain arrival times.
Control signals with uncertain arrival times require a different sort
of amplifier; one that can distinguish between signal and no signal.
The difference between receiving attenuated data signals and receiving
attenuated control signals focuses attention on the fundamental problem
of time in asynchronous systems. Ivan Sutherland will offer some ideas
about the cost of knowing when.
Tutorial. 10:00-12:30, Wednesday, March 16, 2005.
New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems
Phillip Restle, IBM T.J. Watson, and Ken Shepard, Columbia University
Through careful and innovative circuit and interconnect design, global
clock distributions have been successfully constructed into the multi-GHz
range. These networks include tunable trees, grids, and hybrid networks,
including tree-driven grids. Modeling and design of complicated
transmission line effects is required at these frequencies. Adaptive and
active de-skewing circuits have also been successfully employed to
compensate for process variations and (slowly-varying) temperature
variations, often at the expense of degraded clock latency and increased
power-supply noise sensitivity. Despite these past successes, current
techniques for global clock distribution face increasing challenges in
distributing low-jitter clocks in the presence of power-supply noise.
Furthermore, the power dissipated by the clock network is becoming a very
significant fraction of the total power demands of the chip.
Resonant clocking techniques, which resonate the clock capacitance with
on-chip inductance, promise to ease these constraints, enabling lower-power
global clock networks with high immunity to power-supply noise. The
inductance can come from on-chip wires (in the form of traveling-wave and
standing-wave (clocks) or spiral inductor topologies embedded into the
clock wiring network. Topologies that act as either resonant loads or
free-running oscillators will be described using visualizations of
full-wave simulation results.
Asynchronous techniques promise to eliminate clocks entirely. Proponents
may argue that this eliminates issues associated with clock skew, jitter
and power. We will argue a more realistic viewpoint that recognizes that
asynchronous systems must still distribute "control signals." Variation in
the delay of these signals (skew and jitter) presents the same
synchronization overhead as clock skew and jitter in synchronous systems.
Just as "synchronous" designers have borrowed and adapted many asynchronous
techniques (self-timed and self-resetting circuit styles,
source-synchronous links), "asynchronous" designers can benefit from
understanding techniques employed by synchronous designers to distribute
signals across wide areas with high precision in the presence of process,
temperature, and voltage variability.
While fully asynchronous high-speed processors do not seem imminent, there
is a growing opportunity for significant benefit from GALS (Globally
Asynchronous Locally Synchronous) concepts on multiprocessor chips. Due to
uncontrollable across-chip variations in device parameters, power supply,
and temperature, the optimum frequency of each processor varies
independently with time. Power saving techniques such as clock gating tend
to further increase these variations. There may also be different
processors designed for different frequencies on the same chip. Thus the
hidden costs of a single fixed cycle-time global clock are growing. For
fast processors the variations are random but slow compared to the cycle
time, so each processor and asynchronous interfaces might track them. As a
result, robust low-latency asynchronous interfaces could give us many of
the benefits of asynchronous design while still leveraging the huge
investment in synchronous processor design, methodology, and experience.
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