ASYNC 2005
11th IEEE International Symposium on Asynchronous Circuits and Systems

March 13-16, 2005, New York City, USA
Venue: Columbia University



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Venue (unless otherwise mentioned):
  • Davis Auditorium, Schapiro Building (CEPSR), Columbia University


Sunday, March 13, 2005

6:00pm-8:00pmReception and Registration
 Venue: Columbia University Faculty House
(appetizers and dinner)

Monday, March 14, 2005

8:00Breakfast
 
9-9:15
WelcomeChair: Steve Nowick
 
9:15-10:15
Invited Talk 1Chair: Steve Nowick
 Deep Pipelines vs. Risk and Power Walls
Bob Colwell, R.E. Colwell and Assoc., Inc (formerly at Intel)
 
10:15-10:30Break
 
10:30-12:00
Session 1: Circuit Techniques.Chair: Marc Renaudin
 Energy Efficient Surfing
Suwen Yang, Brian Winters, Mark Greenstreet
 GasP Control for Domino Circuits
Jo Ebergen, Jonathan Gainsley, Jon Lexau, Ivan Sutherland
 Design of Multi-GHz Power Aware Asynchronous Pipelined Circuits in MOS Current Mode Logic
Tin Wai Kwan, Maitham Shams
 
12:00-1:30Lunch. Venue: Carleton Lounge, Mudd Engineering Building
 
1:30-3:00
Session 2: On-Chip Networks.Chair: Peter Beerel
 A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-chip
Tobias Bjerregaard, Jens Sparso
 An Asynchronous Router for Multiple Service Levels Network on Chip
Dobkin Rostislav, Victoria Vishnyakov, Eyal Friedman, Ran Ginosar
 An Asynchronous NOC Architecture Providing Low Latency Service and its Multi-Level Design Framework
Edith Beigne, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin
 
3:00-3:30Break
 
3:30-4:15
Industrial Snapshots and Open DiscussionChair: Ken Stevens
 
4:15-4:30Break
 
4:30-6:00
Session 3: Clocking and Synchronization.Chair: Charles Dike
 Register Communication Between two Mutually Asynchronous Domains
Joep Kessels
 Request Driven GALS Technique for Wireless Communication System
Milos Krstic, Eckhard Grass, Christian Stahl
 Self-timed Circuitry for Global Clocking
Scott Fairbanks, Simon Moore
 
On your own for the evening
 

Tuesday, March 15, 2005

8:00Breakfast
 
9:00-10:00
Invited Talk 2Chair: Rajit Manohar
 Proximity Communication and Time
Robert Drost and Ivan Sutherland, Sun Microsystems Laboratories
 
10:00-10:30Break
 
10:30-12:00
Session 4: Design Analysis.Chair: Alex Kondratyev
 Modeling and Verifying Circuits Using Generalized Relative Timing
Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Stevens
 Controlling Event Spacing in Self-Timed Rings
V. Zebilis, C.P. Sotiriou
 Delay Insensitive Coding and Power Analysis: A Balancing Act
Konrad J. Kulikowski, Ming Su, Alexander Taubin, Mark G. Karpovsky
 
12:00-1:30Lunch. Venue: Carleton Lounge, Mudd Engineering Building
 
1:30-2:00
Tribute to Victor VarshavskyChair: Alex Kondratyev
 Speakers: Leonid Rozenblyum and Alex Kondratyev
 
2:00-3:30
Session 5: Design Implementations.Chair: Hans Jacobson
 A Scalable Counterflow-Pipelined Asynchronous Radix-Four Booth Multiplier
Justin Hensley, Anselmo Lastra, Montek Singh
 Continuous Time Digital Signal Processor
Yee William Li, Kenneth L. Shepard, Yannis Tsividis
 BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor
Virantha Ekanayake, Clinton Kelly IV, Rajit Manohar
 
Break, followed by excursion/banquet
 
6:00Excursion: arrive at Chelsea Piers, Pier 61, West 23rd Street (at Hudson River)
 
7:00-10:00Dinner banquet/cruise in New York Harbor (Bateaux New York)
 

Wednesday, March 16, 2005

8:00Breakfast
 
8:45-9:45
Session 6: Test and Reliability.Chair: Marly Roncken
 SEU Tolerant QDI Circuits
Wonjin Jang, Alain J. Martin
 A Multiplexor Based Test Method for Self-Timed Circuits
Frank te Beest, Ad Peeters
 
9:45-10:00Break
 
10:00-12:30
TutorialChair: Prabhakar Kudva
 New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems
Phillip Restle, IBM T.J. Watson, and Ken Shepard, Columbia University
 
12:30-1:30Lunch. Venue: Carleton Lounge, Mudd Engineering Building
 
1:30-3:00
Session 7: Encoding and Synthesis.Chair: David Kinniment
 High Level Synthesis of Timed Asynchronous Circuits
Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris Myers
 Behavior and Synthesis of Two-Input Gate Asynchronous Circuits
Nikolai Starodoubtsev, Sergei Bystrov
 A Unified Coding for Delay-Insensitivity
Fredric Worm, Paolo Ienne, Patrick Thiran
 
3:00-3:30
Closing and AwardsChair: Peter Hofstee and Jose Tierno
 
EveningPost Symposium Activities to be posted shortly
Wednesday evening and through Thursday daytime and evening