AVLSI
ECE 474: Digital VLSI Design
Fall 2003
Announcements (12/16)
 
 
Course Information
 

Instructor: Rajit Manohar (330 Rhodes)

Prerequisites. ENGRD 230; ECE/CS 314.

Credits. 5

Textbook. Weste and Estraghian. Principles of CMOS VLSI Design.

Time/place. TR 1:25-2:40, PH 219

Office hours.

  • Rajit Manohar: TR 10:30-12:00, 330 RH
  • Robert Buels: M 6-7pm, R 3-4, 318 PH
  • Evan Hopkins: MW 12-1, 318 PH
  • Engin Ipek: F 3:30-5:30, 439 RH

Schedule

Newsgroup: cornell.class.ece474

Labs:

  • Lab 1: Introduction (due Sep 11)
  • Lab 2: Combinational logic (due Sep 25)
  • Lab 3: Datapath design (due Oct 16)
  • Lab 4: Control (due Nov 12)
  • Lab 5: Testing + I/O (due Nov 25)


Grading
  The grade for the fall semester will be computed as follows:
  • 55% labs (5%+10%+15%+10%+15%)
  • 10% quizzes (10)
  • 30% prelims (15%+15%)
  • 5% instructor discretion

Academic Integrity. The work you submit in ECE 474 is expected to be the result of your indivdiual effort. You are free to discuss course material, approaches to problems, and details of the system with your colleagues, instructors, and consultants, but you should never misrepresent someone else's work as your own. Permissible cooperation should never involve a student possessing a copy of all or part of another student's design or other work regardless of whether that copy is on paper or in a computer file on a hard disk or a floppy disk. The only exception to these rules is when a project group works together to submit a project.

It is also the student's responsibility to protect his/her work from unauthorized access. For example, do not discard copies of your programs in public places.

Violation of the Academic Integrity Code very often results in failure in the course and permanent notations on your Cornell academic records. If you have any question as to what constitutes ethical behavior, ask the instructor first. We will not be sympathetic to claims of ignorance or misunderstanding of the rules.

 
 
Questions? Contact Rajit Manohar
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