The purpose of this lab is to get familiar with the layout editor
magic and various design tools we will be using this
semester, design a simple circuit, and simulate it using
irsim. For those of you who have not used
irsim before, read the summary of
common commands.
All layout in this class will use the magic technology
file SCN3ME_SUBM.30, which can be specified on the
command line by saying: magic -T SCN3ME_SUBM.30.
Part 1 (tutorials). For the first part of this lab, read and
complete the magic tutorials. Every group member should complete
these tutorials. The commands you will learn will save you many hours
of effort during the rest of the class. The tutorials that you should
read are #1, #2, #3 (pages 1-5), #4, #6, #8. They are available in the
online documentation for magic.
Part 2 (layout). Use the layout editor magic to draw a
chain of three inverters with inputs labelled i1,
i2, i3 and outputs o1,
o2, and o3 respectively. Connect
o1 to i2 and o2 to
i3. Make each inverter as small as possible (in terms of
the width and length of each transistor), and your overall layout
as compact as possible. The width of each transistor should be at least
4 lambda.
Save your design in file inv.mag (do not use hierarchy
for this lab), and extract your circuit (tutorial #8) to generate file
inv.ext.
Part 3 (CAST files).
Write a CAST file called inv.cast that describes the three inverters using production rules. Your file must import 474/globals.cast which contains the definition of global symbols. As an example of the way CAST supports production rules, a two-input NAND gate would be written as follows:
define nand2() (node a, b, c)
{
prs {
a & b -> c-
~a | ~b -> c+
}
}
Note that all variables in the pull-up network are negated, whereas
all variables in the pull-down network are non-negated.
Define threeinv() (node i, o) that contains the three
inverters you designed in part 2, with i connected to
i1, and o connected to
o3. Simulate this CAST file with IRSIM by creating a test
file test_inv.cast that instantiates a copy of
threeinv. Save your IRSIM test script in
inv_cast.cmd.
Instructions on simulating CAST files with IRSIM can be found here (these are the same instructions used for
ECE/CS 314). Make sure you set Vdd and GND
to the right values in the IRSIM test script.
Part 4 (simulate layout).
Generate files
inv.sim and inv.al by saying ext2sim
inv.ext. Simulate your circuit using irsim by
saying: irsim ami30.prm inv.sim inv.al. Save the test
script for your circuit in file inv.cmd.
Your layout should use Vdd! to label the power supply,
and GND! to label ground. Ensure that the substrate is
connected to the appropriate power supply by using substrate contacts
(material name: psc and nsc for p substrate
contact and n substrate contact). To see the substrate, place the box
over your layout and say: :cif see CWN or :cif see
CWP to see the different wells. To erase the white feedback
paint, use the command :feedback clear.
Make sure you set Vdd! and GND! to the right
values in the IRSIM test script.
Part 5 (lvs).
You must also check that your physical layout implements the
production rules in your CAST file by using the program
lvs. lvs is a tool that checks whether the
extracted layout matches production rules.
To run lvs, you need to extract your layout and also
generate a production rule file from your CAST files. To generate
a production rule file from your CAST file, say:
cast2lvs inv.cast threeinv > threeinv.prs
To compare production rules against your layout, say:
lvs -dDE inv.ext threeinv.prs
For more information on lvs, try man lvs.
For lvs to match your layout against production rules,
the names you use for nodes in your layout MUST MATCH the names you
use in your CAST file. In addition, cell ids must match the names used
to instantiate defintions in CAST for hierarchical layout.
Part 6 (well-plug checking).
You must run the following on each
.mag file that has transistors in it (in this case just inv.mag):
wellcheck file.mag
If the program is silent, your design passed the check. If it isn't,
it will output a file that has shows you regions containing wells
that haven't been plugged. Note: this program is paranoid, so
a well must be plugged in the SAME CELL as the one in which it is drawn.
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