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The following is a schedule of the quizzes and exams for the class
(Ln = lab, Qn = quiz), along with a tentative schedule
of the topics we will be covering. Readings from the textbook will
be posted on this site (posted as section numbers) as the class progresses. The two prelim dates
are highlighted.
Each quiz will be 10 minutes in length and will test knowledge of
material from class that was covered after the previous quiz
(typically 1 weeks worth). The two exams will be in class and
cumulative.
| Date | Topic | Reading | Other |
| R Aug 28 | Introduction | 3.{1,2} | |
| T Sep 2 | From physics to switches | | |
| R Sep 4 | Switching networks | 1.{4,5}, 5.4.1 | L1 out |
| T Sep 9 | Dynamic logic, pseudo-NMOS | 5.4.3 | Q1 |
| R Sep 11 | Concurrency management | | L1 due; L2 out |
| T Sep 16 | Clocking schemes | 5.5.{1,2} | Q2 |
| R Sep 18 | Charge sharing, charge pumping, registers | | |
| T Sep 23 | Precharge logic, domino logic | | Q3 |
| R Sep 25 | Retiming | | L2 due; L3 out |
| T Sep 30 | Floorplanning | | Q4 |
| R Oct 2 | PLAs, datapath design | | |
| T Oct 7 | Datapath design | | Q5 |
| R Oct 9 | Memory design | | |
| T Oct 14 | - Fall break - | | |
| R Oct 16 | Memory design | | L3 due; L4 out |
| T Oct 21 | In class prelim #1 | | Prelim 1 |
| R Oct 23 | Clock distribution, I/O, guard rings, latchup | | |
| S Oct 25 | | | L4 out |
| T Oct 28 | Transistor sizing | | Q6 |
| R Oct 30 | Transistor sizing | | L5 out |
| T Nov 4 | Testing | | Q7 |
| R Nov 6 | Testing | | |
| T Nov 11 | Skew-tolerant domino, ripple-reset domino | | Q8 |
| W Nov 12 | | | L4 due |
| R Nov 13 | Self-resetting domino, output prediction logic | | |
| T Nov 18 | Energy | | Q9 |
| R Nov 20 | Energy | | L5 due |
| M Nov 24 | | | L5 due |
| T Nov 25 | Metastability | | Q10 |
| R Nov 27 | - Thanksgiving - | | |
| T Dec 2 | In class prelim #2 | | Prelim 2 |
| R Dec 4 | Scaling | | |
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