||
|| ECE 474 lab3 validation script
|| NOTES: 
||   You should see no errors here, except for possibly Vdd! and GND! definition complaints
||   This script must work for simulating both your layout and the CAST.
||   In addition, your CAST must LVS against the MAGIC.
||   The actual script that will be used in grading will be different from this script,
||   but the signals will be named identically and the initialization will be identical.
||

print Starting validation script...

|| initialize the rail voltages (this may cause complaints but that is ok)
h Vdd
h Vdd!
l GND
l GND!

|| set up signal vectors
vector IN in[{7:0}]
vector OUT out[{7:0}]
vector G g3 g2 g1 g0
vector R0 r01 r00
vector R1 r11 r10

|| set up waveform view
ana IN OUT G c s l w0 R0 w1 R1 en_fblock en_shift en_addsub ext_l ext_r

|| set up the control signals to all be disabled by default
set G 0000
set R0 00
set R1 00
l w0 w1 en_fblock en_shift en_addsub ext_l ext_r


||
|| 1) load constant values into the registers
||

|| r0 = 0x83
set IN 10000011
h ext_l w0
s
l w0
s

|| r1 = 0x7F
set IN 01111111
h w1
s
l ext_l w1
s

||
|| 2) read the value of each register using the external output
||

|| read r0 (should be 0x83)
set R0 01
h ext_r
s
assert OUT 10000011
set R0 00

|| read r1 (should be 0x7f)
set R1 01
s
assert OUT 01111111
l ext_r
set R1 00


||
|| 3) adds two values and stores the result in a register
||

|| add the values in the two registers (show r0 result value on output)
l c
set R0 01
set R1 10
h en_addsub
s
l en_addsub
set R0 00
set R1 00
h w0
s
l w0
set R0 01
h ext_r
s
assert OUT 00000010
l w0 en_addsub ext_r
set R0 00


||
|| 4) shifts a value and stores the result in a register
||

|| shift the value in r0 right by 1 and store result in r0 (show r0 result value on output)
h s en_shift 
l l
set R0 01
s
l en_shift
h w0 ext_r
s
assert OUT 00000001
l w0 s en_shift ext_r
set R0 00

||
|| 5) computes some logical function using the two registers as inputs
||    and stores the result in a register
||

|| perform an XOR of r0 with r1 and store result in r0 (show r0 result value on output)
set G 0110
h en_fblock
set R0 10
set R1 01
s
l en_fblock
set R1 00
set R0 01
s
h w0 ext_r
s
assert OUT 01111110
l w0 en_fblock ext_r
set R0 00
set R1 00

print Validation script completed.
print If no assertions were broken, you are in good shape :)