Announcements

• The prsim command random will run the production rules with random timings, and also ensure that the sources provided in the standard environment will produce random outputs. Simulating your production rules using prsim with random will help you debug stability/interference problems as well.

• Presentation (ARM): Joel Avrunin, Brian Silverstein, Ilyas Elkin, Larry Pellach.

• Presentation 1 on the 28th (Alpha): Benjamin Pollock, Jeffrey Tyhach, Maheen Samad, John Gorman.
• Presentation 2 on the 28th (PPC): Brian Ellyson, Donald Chai, Hyun Lee.

• Part 4 of the project posted. Note that prlint uses a very slow (exponential time) algorithm. Make sure you test small processes independently. If the production rules for individual processes are stable and non-interfering, and all processes follow handshake protocols, then the production rules for the entire computation will be stable and non-interfering too.
• prlint might warn you about nodes like Vdd and GND having one transition only. This is correct. :-)
• It might be a good idea to try some simple processes like splits and merges before you begin your project production rules.

• Presentation 1 (Asynchronous Alpha w/ subliminal message): Abraham Heifets, Stephen Lee, David Chen
• Presentation 2 (Asynchronous Alpha,64 bit): Arvind Kumar, Kevin Ferguson, Jintadhee Sudasna, Travis McLeskey

• Presentation evaluation form online
• Presentation 1 (Asynchronous Alpha): Clint Kelly and David Biermann
• Presentation 2 (Asynchronous PowerPC): Gee-Hwan Chuang, Kay Khoo, Yuan Lin, Philip Ching

• Deadlines extended. Project part 3 due date: Nov 14th; Project part 4 due date: Dec 8th

• I've provided a sample project report.
• The simulator supports bitfield extraction. The syntax is variable{lo..hi} or variable{bitnum}. The bitfield specifications can only consist of integer constants (or simple constant expressions).

• LaTeX macros for production rules and CHP: (style file, additional required file). Sample input:

  \documentstyle[prs]{article}
  \begin{document}
  \begin{prs}
  a -> b+
  ~a&c->q-
  \end{prs}
  
  \begin{csp}
  *[[#{X} -> X!a
   []#{Y} -> Y?a
   ]]
  \end{csp}
  
  \end{document}
  

• Clarifications for HW#4 (announced in class): unless otherwise specified, use an active protocol on input ports and a passive protocol on output ports. If the width of a variable is not specified, assume that it is 1-bit wide.

• Part 3 of the project posted. Note that the due date is November 7th. This part is significantly more difficult than any of the earlier parts, so please start working on it ASAP.

• HW3 grades posted.

• HP and Intel are visiting campus. If you're interested, HP is going to hold an info session and Intel has the following job announcement

• The simulator now supports logging in hex format. To print out an integer in hex format instead of decimal, use hex(integer) instead of the integer.

• Examples covered in class (lr, eager stack)

• The homework is now due on Tuesday Oct 3.

• I will be talking about the CHP simulation environment in class tomorrow.

• Add the following line to your .cshrc:

  
  	setup 571
  

• The assembler documentation is available on-line; you might want to look at it if you have questions about assembler syntax.

• All solutions to HW2 must contain the CHP description for each process.
• Electronic submission instructions for deadline 1 added to the project description.

• Detailed solutions to HW1 posted.

• Solutions to HW1 posted. They will be updated soon to include more information (esp. problem 2), but the CHP for problem 4 is correct and you can use it as the starting point for HW2.

• The next HW will be handed out on Thursday.

• Created a FAQ for the class.

• Homework 1 handed out today. Due 1 week from today in class at the beginning of class.
• I've created a class alias 571class at csl.cornell.edu. You can send e-mail to this alias and it will be broadcast to the entire class. Use this if you don't have a group yet, are trying to find documentation, etc etc.
• If you want to find binaries of programs for different architectures (to disassemble them and look at assembly code, for instance), check out the NetBSD home page. They have precompiled binaries for NetBSD on a number of different architectures. (Note that objdump and as from the binutils package are architecture and OS specific.) The NetBSD page also has pointers to documentation for various architectures.

• I have a VAX architecture reference manual in my office that is available for anyone who wants to look at it. The first edition of the Hennessy and Patterson book on computer architecture also has a VAX reference in the appendix.
• You may choose the SPARC ISA for your processor.

• There are five copies of notes for this course in my office. You can pick them up and make a copy for yourself if you want them. The notes correspond pretty closely to what I cover in the class.
• I have three architecture reference manuals in my office: ARM, Alpha, and a particular PowerPC processor. You may borrow these for a few days (as other groups might want to do the same).

• Project deadline 1 posted. Start now!
• Course accounts created.

• Sign up!
• Lecture notes posted for next week.

• Web site created. Please check this page regularly.