[Magic-dev] parasitic resistances from layout

[riaz naseer]

Hi All,

I have done some experimentation with an inverter.
I am doing experiments for assessing how the parasitic resistances will affect the delay.

Here is my problem that I am not able to understand:
The simple inverter circuit without extracting resistors runs faster than the version with extracted resistances.
(There is no difference for the capacitor values in the netlist). My expectation is that a circuit with having more resistors should incur more RC delay and hence should be slower.

I will greatly appreciate if anyone can shed some light on this.

Thanks and Regards,

Riaz Naseer