[Magic-dev] RE: Broken nets

[Satpal Singh]

Dear Tim,

Thanks for your quick reply.

I do agree with you that magic is probably quiet robust, I have been using 
magic 6.4 and then 6.5 since 1995 and never had this problem before, and I 
actually love magic to the point where I walked away from other tools.

I am not doing anything different from what I have been all these years, 
and don't understand how labels can get copied from one cell to another, I 
have always used same label, for example "vin" and "vout" in numerous of my 
cells where the design is hierarchical. Also, in one instance, i had m2 
track of a parent cell overlap by a few lambdas the m2 within a cell, and 
yet the track in the parent cell came out in the extracted net list as 
"Floating".

In the past, I have extracted the design, then used "ext2spice" to generate 
a net list on which I have run the simulations and do the LVS, but if I 
cant even get a proper net list out, I cant do LVS.

Please advise, I will greatly appreciate your help here.

Satpal


At 11:56 AM 3/15/2005 -0500, R. Timothy Edwards wrote:
>Dear Satpal,
>
> > I recently downloaded Magic 7.1 and am using the tech file
> > SCN3ME_SUBM.30.tech27 to design for AMI 0.5 um process. On extraction
> > (ext all) and running ext2spice to generate a netlist, I occasionally
> > (not always) find that a single net in the layout has been broken
> > into 2 different nets in the spice file, this leads to the failure of
> > simulation.
>
>There are a number of reasons this sort of thing can occur.  The
>reason that they seem "random" is that the extractor is not to
>blame---the extraction algorithm in magic is surprisingly robust---
>but there are a number of other subtle errors that can occur.
>
>One of them, which may have caused at least one of your broken
>simulations, is that labels can get copied from one cell into another,
>and end up on separate layer types (e.g., metal1 and metal2) that
>are not connected.  Extraction will short nets having the same
>(labeled) name.
>
>Usually it is a good idea to ensure that the circuit layout is correct
>by doing LVS (layout vs. schematic) as well as extraction+simulation.
>
>
>                                         Regards,
>                                         Tim