[Magic-dev] RE: "extra" nodes from magic extract

[R. Timothy Edwards]

Dear Piyush,

> So my question is that where do these nodes "a_n36_n9#" and
> "a_n1_n3#" etc come from?

Magic's names for unlabeled nodes can be interpreted as:

	(plane_short_name)_(x_position)_(y_position)#

where the 'plane short name' is found in scmos.tech but generally
follows the convention w=well, a=active, m1=metal1, etc., and "n"
in front of a number means negative.

So you can track down the node "a_n36_n9#" by looking for the
layer on active (diffusion or poly) at position (-36, -9).

There really are 12 nodes in your layout.  In addition to the
labeled nodes, two transistors have unconnected ends (which were
presumably intended to attach to "test", perhaps by the misplaced
piece of metal1, which gets counted as another node).  There is
also one internal node in the AND gate between the two nMOS
transistors, and then there are the two wells which will be
considered isolated until connected to vdd with a "nsc" contact.

It is not necessary to have drawn wells for an extraction, but it
is necessary to have the well and substrate contacts in a circuit
if you want it to work correctly.  If you put both nwell and pwell
and connect both with contacts, you will get the proper substrate
(bulk) contacts to the transistor devices in the netlist.  If you
leave the wells undrawn, you will get the default nodes "Vdd!" and
"Gnd!" in those positions, which must be equated somehow with
the power and ground networks.  In magic-7.1, you would need to
label your power and ground networks "Vdd!" and "Gnd!", resepectively.
In the Tcl/Tk versions of magic-7.2 and 7.3, you can just put the
Tcl commands "set VDD vdd" and "set GND gnd" to denote that your default
well and substrate nodes are connected to those nets (which is,
of course, a misleading idealization if you don't have the well
and substrate ties).

					Regards,
					Tim