[Magic-dev] Extraction of resistance and capacitance?

[Ramakrishnan Krishnan]

Hi all,

I have few doubts regarding the extraction of resistance and capacitance in MAGIC.

Few questions regarding them are

1. How is AD,AS,PD,PS calculated from the .EXT file and put in .SP file?

2. The capacitance values listed for a node in the .EXT file is extracted to .SP file and shows the caps between the node and ground.
What happened to the resistance of the node ? For example in the follwoing .SP file and .EXT file, the 2 caps C0 and C1 for o1 and vdd are listed in the .SP file while what happens to the resistances of the nodes o1,in etc in the .SP file while neing extracted from .EXT?


.ext file
----------

timestamp 1115769301
version 5.0
tech mmi07
scale 1000 1 1
resistclasses 115 115 115 115 115 115 115
node "gnd" 2 570 406 55 ndif 0 0 3848 53 0 0 0 0 0 0 0 0 0 0
node "gnd" 2 621 56 54 ndif 0 0 4145 58 0 0 0 0 0 0 0 0 0 0
node "out" 3 1115 449 55 ndif 0 0 9576 102 0 0 0 0 0 0 0 0 0 0
node "vdd" 3 1018 406 241 pdif 0 0 8272 94 0 0 0 0 0 0 0 0 0 0
node "vdd" 3 1086 56 240 pdif 0 0 8656 100 0 0 0 0 0 0 0 0 0 0
node "o1" 8 2210 99 54 ndif 1961 45 13360 163 0 0 0 0 0 0 0 0 0 0
node "in" 5 948 47 183 poly 1961 45 2824 48 0 0 0 0 0 0 0 0 0 0
fet nfet 442 55 442 55 700 214 "GND!" "o1" 14 0 "gnd" 100 0 "out" 100 0
fet nfet 92 54 92 54 700 214 "GND!" "in" 14 0 "gnd" 100 0 "o1" 100 0
fet pfet 442 241 442 241 2100 614 "Vdd!" "o1" 14 0 "vdd" 300 0 "out" 300 0
fet pfet 92 240 92 240 2100 614 "Vdd!" "in" 14 0 "vdd" 300 0 "o1" 300 0

.sp file
---------

* HSPICE file created from test2.ext - technology: mmi07
*
* Header file for an ASIC circuit HSPICE run
*
.option post
.option post_version=9007  $ mmi's nst program require this
.option ACCT=1 BRIEF=1
.option NUMDGT=8 MEASDGT=8 $ for output printing
.option ACCURATE           $ this is for transient analysis only
*
VVDD Vdd 0 1.00
Vin in 0 PWL 0.01NS 0.00V 1.00NS 0.00V 1.01NS 1.00V 2.00NS 1.00V
+ 2.01NS 0.00V 3.00NS 0.00V 3.01NS 1.00V 4.00NS 1.00V
+ 4.01NS 0.00V 5.00NS 0.00V 5.01NS 1.00V 6.00NS 1.00V
+ 6.01NS 0.00V 7.00NS 0.00V 7.01NS 1.00V 8.00NS 1.00V
.TRANS 0.1NS 8.00NS
* HSPICE file created from test2.ext - technology: mmi07

.option scale=0.01u

m0 o1 in vdd Vdd pch  w=300 l=7
+ ad=13360 pd=163 as=16928 ps=194 
m1 out o1 vdd Vdd pch  w=300 l=7
+ ad=9576 pd=102 as=0 ps=0 
m2 o1 in gnd GND nch  w=100 l=7
+ ad=1961 pd=45 as=0 ps=0 
m3 out o1 gnd GND nch  w=100 l=7
+ ad=0 pd=0 as=0 ps=0 
C0 vdd GND 2.1fF
C1 o1 GND 2.2fF

** hspice subcircuit dictionary
*
* Tail file for an ASIC circuit HSPICE run
*
.protect
.LIB '/home/users2/kyusun/tool/model/libcmos007ucb.sp' CMOS1
.unprotect
* 
.end


Thanks in advance.

Regards,

Ramki.K




Ramakrishnan Krishnan,
Graduate Student,
Dept of Electrical Engg,
Pennsylvania State University,University Park,
State College,
PA 16801.

Ph : 001-814-237-4538
Email : ruk142 at psu.edu
        ram_krec at yahoo.com-------------- next part --------------
An HTML attachment was scrubbed...
URL: http://vlsi.csl.cornell.edu/pipermail/magic-dev/attachments/20050517/30547054/attachment.html