[Magic-dev] Using magic with STM 90nm process???

[R. Timothy Edwards]

Dear Clint,

> Do you think it would be possible to change the design rules for a
> 90nm process to make them slightly more conservative and therefore
> make them easier for magic to check?

Yes, absolutely.  I started out this way with the TSMC 90nm tech
file, but I ended up working on a project where I was tweaking the
layout of a vendor-made standard cell, so to properly read in the
vendor GDS, I needed to be on minimum grid with liberal design rules.
Oddly, the vendor GDS was drawn on rules more liberal than the TSMC
DRC document allows---I don't know how they get away with that.

The TSMC documentation had a slew of "absolute" rules and another
slew of "recommended" rules.  I found, in general, that if I enforced
the more conservative "recommended" ruleset, it was much easier to
get magic's design rule checker to match.  However, there are still
complicated rules like "spacing A to B must be X except when A is
closer than distance Y to layer C", etc., etc.  I know of a way to
capture most of these rules using a generic form of the method I
implemented for checking wide-metal-spacing rules, but I haven't
coded it yet.  I also have come up with a method for detecting
violations of spacing rules on catecorner N+/P+ implant layers and
other auto-generated mask layers, which tends to be a problem with
magic in that these sort of errors should not affect circuit behavior,
but vendors will now reject GDS data that contains them---i.e., it
becomes increasingly difficult to waive these drc violations, or at
least increasingly cumbersome to fill out all the waiver forms.

					Regards,
					Tim

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| Dr. R. Timothy Edwards (Tim)   | email: tim.edwards at multigig.com     |
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