[Magic-dev] Using magic with STM 90nm process???

[R. Timothy Edwards]

Dear Erwin,


> We have 
> elected to use Mentor Graphics Calibre to check the design rules, since 
> we had a Calibre deck available which had been verified with QA cells 
> (quality assurance). I think it is a major project to code the 90nm 
> rules in Magic, fabricate suitable QA cells, and then proof the DRC 
> rules with the QA cells, and make sure the rules check identically to 
> the decks already available. To start, have a look at the bond pad 
> design rules...

I have done exactly that, and yes, it is a royal pain.  However, one
can capture 90% of rules in the magic tech file without too much work,
and the layout is still much easier in magic than with any other tool
(at least, most people seem to think so), particularly if you can work
on a lambda grid in magic instead of a minimum-dimension (e.g., 0.1 or
0.01 um) grid.

I have managed to do several chips in the last couple of months by
using Cadence to generate some of the "p-cells", like bipolar
transistors, pads, varactors, copyright text, etc., and importing
them into magic using the "gds readonly true" and "gds rescale false"
commands that I coded recently.  Using this method, the "view" of
the subcell in magic is in magic's layers but the GDS of the subcell
is copied directly from the vendor GDS into the final GDS file.  That
lets me do final chip assembly in magic (using TCL scripts, usually).
I insist on using Calibre for final DRC but usually I can get magic's
DRC to be near-perfect after numerous iterations.

					Regards,
					Tim

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