[Magic-dev] Re: Help on magic extraction

[R. Timothy Edwards]

> Is there anyway to extract magic layout with corners such as 
> temperature

Normally, the design kit (usually Cadence) that comes from the
semiconductor foundry will contain SPICE models at the primary
process corners.  Normally this would mean separate models for
FAST, FAST-SLOW, NOMINAL, SLOW, and SLOW-FAST.  Temperature is
handled separately, since all models should be valid over the
continuous temperature range of interest (commercial/industrial/
military minimum and maximum values, and of course room temperature
nominal).  Neither the models or temperature is related to the
extraction, at least as far as *modeled* devices are concerned.
To get from an extracted SPICE deck from magic to a simulation,
you need to insert the models along with the rest of a testbench
setup for SPICE, so at that time you would reference the proper
corner model and set the proper corner temperature.

For *unmodeled* devices, namely the parasitic capacitors and
unmodeled resistor and capacitor devices (using my newer extraction
algorithms), if you wanted to go to the trouble, you could add
separate style sections in the Magic technology file representing
each process corner, and appropriately adjust area and perimeter
capacitances, sheet resistances, etc.  I have never seen this done.

					Regards,
					Tim

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| Dr. R. Timothy Edwards (Tim)   | email: tim.edwards at multigig.com     |
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