[Magic-dev] Dumb Newbie question (a.k.a. digital design flows)

[R. Timothy Edwards]

Dear Bob,

 > I am trying to do some custom asic/ ic design work and was looking at using
 > Magic and related tools to do so. What i want to do is this
 >
 > VHDL/Verilog -> Placement -> FPGA.
 >
 > Its been a little while since I did this and we used Mentor Graphics in
 > school. Am I even on the right track with using these tools for that? If I
 > am what other tools besides magic would I need. I am having problems
 > figuring out how the data flows between the tools. Any help would be greatly
 > appreciated.

This is not a "dumb newbie" question at all.  It's central to the whole
problem of open-source EDA tools in the sense that this flow practically
does not exist at all in open-source tools.  I have been working on this
problem a lot over the past year, from which experience you can find a
bit of information at

	http://opencircuitdesign.com/verilog/index.html

I can assure you that the flow works, as I have put together some
fairly complicated digital blocks from Verilog and XCircuit schematics
for MultiGiG production chips, and they have been manufactured, tested,
and verified on the Jazz 0.35um SiGe process with the Jazz standard
cells (which are probably Artisan/ARM or derived from them) and on the
IBM 0.18um SiGe process using the IBM standard cells that come with the
design kit.  This does not mean that the process is convenient, or easy,
or will work at all on your system or for your target process.  There
are several hurdles including compiling programs like SIS, VIS, and
TimberWolf, which do not have especially good support for all processor/
OS types.  The other hurdle is getting Magic to do auto-routing, the
pain of which varies greatly depending on the specifics of each fabrication
process.

Since posting the web page mentioned above, I have solved a few issues like
adding pre-processing and post-processing scripts to VIS and SIS to
handle multiple clock domains and initialization of set/reset flops.
Still, it's a long way from where I would like it to be.

Having worked heavily with Verilog for about a year now, I have reached
the conclusion that it is a lousy way to define circuitry (apart from
the fact that it is a much better way to define circuitry than VHDL,
which is even lousier).  I've found it much easier to define (relatively
simple) systems with schematics, and restrict Verilog mostly to big
combinatorial logic blocks, for which it is well suited.

I assume that since digital flows are used to build microprocessors,
the software tools to manage the flows are highly valued, very lucrative,
and therefore are rarely to be found in the public domain.

					Regards,
					Tim

+--------------------------------+-------------------------------------+
| Dr. R. Timothy Edwards (Tim)   | email: tim at opencircuitdesign.com    |
| Open Circuit Design, Inc.	 | web:   http://opencircuitdesign.com |
| 22815 Timber Creek Lane        | phone: (301) 528-9364               |
| Clarksburg, MD 20871-4001      | cell:  (240) 401-0616               |
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