[Magic-dev] Layout in sub 100-nm technology

[R. Timothy Edwards]

Dear Haran,

 > I understand that at present Magic supports feature sizes till 1 nanometer.

A common but unfortunate misconception.  Magic can support feature sizes
infinitesimally small due to the scalable nature of the CIF specification.
With GDS files, magic versions up to 7.4 can handle data on grid points on
1 nanometer spacing (which is not quite the same thing as a 1 nanometer
feature size!), while version 7.5 can handle data on grid points on 1
angstrom spacing.

 > So, how does one draw layouts in 65 nm, 90 nm processes? Obtain permission
 > and get the related tech files?

Magic uses an internal database of unscaled, dimensionless internal
units.  The technology file defines a "cifoutput" section (also good for
GDS output) which translates internal units to physical units when
generating output.  Having a "cifoutput" style declare "scalefactor 65
nanometers" will give you 65 nm output.

By the way, note that if you have a 65nm process and you want to draw
something at half lambda, it ends up at 32.5nm, which necessitates moving
to angstroms to represent such coordinates in integer units in a GDS output
file.  This is why magic supports "angstroms" in the scalefactor line, not
that any foundry is going to allow data on a 1-angstrom grid any time soon.

 > What does this scalefactor mean? Is it possible to draw the layout in say
 > 180 nm process and then scale it down to 65 nm?

The "scalability" of CMOS processes has always been more theoretical
than practical.  However, Magic was designed to do just what you said,
to read in a database at, say, 180nm, and write it back out at 65nm,
with any necessary subtle geometric manipulations necessary because
no process ever scales perfectly (at least none that I have ever
encountered).

						---Tim

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