[Magic-dev] Dumb Newbie question (a.k.a. digital design flows)

[R. Timothy Edwards]

Dear Leandro,

> And what is your opinion about describing circuits using functional
> languages like Haskell?
> I'm starting to study it, so I can't tell you much now, but there is a
> interesting site that addresses the subject:
> http://www.funhdl.org (Functional HDL)
> they are developing atom, a Hardware Description Language embeded in haskell.
> There is also a similar system called Lava where you could describe
> your circuit and then get a verilog output for xilinx fpga or
> "generic" verilog.

I don't have much of an opinion because I'm not especially familiar
with functional languages.  I took a quick look through the list, and
please correct me if I'm wrong, but the offerings I saw mostly compile
into C, Verilog, VHDL, and occasionally some limited format like Xilinx
logic blocks.

While I do have many complaints about how Verilog is designed, it doesn't
really help if the functional description ends up in Verilog format,
since the real problem for VLSI design is getting from Verilog format
to a standard-cell or transistor-level description.  The only open-source
tools that I have been able to obtain that can do this are the Berkeley
VIS and SIS tools.  Most of the work in coding these tools appears to
have been devoted to the problem of logical optimization of combinatorial
blocks.  Unfortunately, these tools are extremely limited in their
capability beyond handling combinatorial blocks.  Every circuit can run
off of at most one clock, and that clock must be an input to the system
and cannot be derived from any logic.  Also, only the positive edge of
that clock can be handled.  Level-sensitive latches are unknown, as are
tri-state devices.  Just to get a tool flow that could handle the
simplest "always @(reset) begin. . ." block, I had to preprocess the
Verilog, remove the reset procedure block so that VIS/SIS could handle
the resulting Verilog, generate a standard cell netlist with VIS and
SIS, then post-process the netlist to replace the standard flops with
set and reset flops as necessary to produce all the reset conditions.
Since that only solved about half of my problems, I eventually abandoned
Verilog altogether for some of the blocks that required complicated
timing and drew them as xcircuit schematics.

If it weren't for the fact that I have a dozen other projects in mind,
I'd like to embark on a project to develop a tool that converts
Verilog, or functional code, or whatever makes the most sense, into
some low-level description like transistor n- and p-stacks, and then
either generates a transistor-level circuit or else maps the transistor
stacks into standard cells.  But if there were a halfway decent solution
out there that costs less than a $100k+ Synopsys license, I wouldn't
bother.

					Regards,
					Tim

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| Dr. R. Timothy Edwards (Tim)   | email: tim at opencircuitdesign.com    |
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