[Magic-dev] Problems extracting parasitic resistors with Magic

[R. Timothy Edwards]

Dear Graham,

>    Is anyone using the resistance extraction capabilities of Magic for
> individual cell extraction? I cannot get it to work. My flow is in the script
> below, where the commented parts should enable extracted resistors. I am using
> my own tech file. The layout has explicitly drawn pwell. For the inverter
> example, both the nwell and pwell are connected to vdd and vss with substrate
> contacts.
>    Below that are the results with and without resistance extraction for a
> simple inverter.
> 
>    There are at least two problems with the resistance extracted spice deck.
> 1/ The nmos drain is connected to floating node vss.t0
> 2/ The nmos area and perimeter values haven't been extracted.

> M1000 vdd a z.t0 vdd pmos w=0.99u l=0.11u
> + ad=0.553575p pd=3.3u as=0p ps=0u 
> M1001 vss.t0 a z.t1 vss nmos w=0.495u l=0.11u
> + ad=0p pd=0u as=0p ps=0u 
> C0 vdd a 0.015fF
> R0 z.t1 z.t0 3
> R1 z.n0 z.t1 3
> C1 a gnd! 0.021fF **FLOATING
> C2 vdd gnd! 0.016fF
> C3 vss.t0 gnd! 0.086fF
> C4 z.t0 gnd! 0.089fF
> C5 z.t1 gnd! 0.114fF
> C6 z.n0 gnd! 0.006fF **FLOATING

I agree that the floating node vss.t0 is an error, and probably has
something to do with the node being a supply node.  I recall that
"extresist" is not supposed to break up power supply nets by default,
and I will have to look into this problem (if you could send me the
exact layout, that would help).

The missing area and drain is due to magic's lumping the node
parameters.  It has put all of the node area and perimeter onto
one transistor, and left the other zero.  There is a distributed
mode that splits the values between transistors.  Supposedly, the
declaration of source/drain area and perimeter suffice for correct
simulation, though I have not looked at it in enough detail to vouch
for that.

Unless you are trying to get a very, very detailed extraction, I advise
you not to use the "resistor tee" setting.  The purpose of this
(experimental and only lightly tested!) option is to account for the
capacitance between a semiconductor resistor (e.g., polysilicon, active,
or n-well) and substrate.  One way to do this is to split the resistor
in half, and put the equivalent capacitance in the middle.  Otherwise,
the capacitance of the resistor material goes unaccounted for in magic
(note, however, that like transistor gates, this capacitance may be
accounted for in a SPICE semiconductor resistor model, but won't be in
the standard model-less resistor).

Finally, note that the "gnd!" substrate node is a default node name for
the substrate net.  Magic version 7.5 allows the default node to be
specified as a Tcl variable, usually "$GND", so that "set GND vss"
would be the appropriate Tcl command to declare the node "vss" to be
the same as the default substrate.  Undoubtedly I should code in a
proper substrate node extraction, but for now, the variable setting is
a little better than relying on global node names.  Note that "set GND
vss" only works if "$GND" appears in the tech file's extract section
definition for an nMOS transistor, and that its only effect will be
the substitution of all occurrances of "gnd!" above with "vss".

Hope that explanation helps.

					Regards,
					Tim

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| Dr. R. Timothy Edwards (Tim)   | email: tim at opencircuitdesign.com    |
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