[Magic-dev] Extracting cross coupled capacitance with sidewall
Graham Petley
graham.petley at vlsitechnology.org
Mon Dec 17 10:45:14 EST 2007
Hallo,
Back on Feb 18 this year I queried Magic extraction for cross coupling
capacitances when there is a shielding wire between.
http://vlsi.cornell.edu/pipermail/magic-dev/2007/000376.html
If we take three wires, a,b and c below, then the coupling capacitance
between a and c is the same whether b is present or not.
+---------------------+
a | |
+---------------------+
+---------------------+
b | |
+---------------------+
+---------------------+
c | |
+---------------------+
I finally checked up on this. The extraction command which handles coupling
caps is sidewall and it does behave as above. I think this is wrong. I checked
the behaviour with the supplied tech files.
-for scmos.tech the sidewall checks are zeroed out by setting the threshold
distance to 0 with option
sidehalo 0
- for scmos8m.tech sidehalo has been set low at 8 which I think corresponds to
0.72um in a 0.18um techno. This is little more than a track separation, and two
parallel wires like a and c above will be separated by more than 0.72um.
So in conclusion, the sidewall extraction option does not work properly in
Magic and the workaround is to make sure the value of sidehalo is less than
(2*track_pitch-wire_width) for the tightest pitch, probably poly.
The sidewall syntax is
sidewall intypes outtypes neartypes fartypes cap
and for poly is like
sidewall (poly,polyct)/a ~(poly,polyct)/a ~(poly,polyct)/a (poly,polyct)/a 14
Intypes and fartypes are the same, poly in this case, and outtypes and
neartypes are the expression not poly. However even if there is some poly in
between, so the sidewall expression is not true, capacitance is extracted
anyway which doesn't seem a correct operation.
Best regards, Graham Petley
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