[Magic-dev] Extraction questions for nfet and pfet

[Graham Petley]

Hallo,

   I have seen that the sidewall cap of transistor gate (nfet or pfet) to other
gate or poly isn't included in the supplied tech files. IMHO there should be
statements in the extract section like

sidewall (*poly)/a ~(*poly)/a ~(*poly)/a (*poly)/a         5.0
sidewall (nmos)/a ~(nmos,*poly)/a ~(nmos,*poly)/a (nmos)/a 5.0
sidewall (pmos)/a ~(pmos,*poly)/a ~(pmos,*poly)/a (pmos)/a 5.0

if the poly sidewall cap is 5aF/lambda. (I use nmos and pmos as synonyms for
nfet and pfet.)

   I have also been looking at the sideoverlap cap (fringing) of poly to
diffusion, which means actually gate to diffusion. I couldn't find anywhere on
the web or in my book collection whether this value is handled by the MOS spice
model or by the extraction tool. For a typical 0.13um techno, the spice model
has CGSO=CGDO = approx 500aF/um which is the gate to s/d overlap cap. This
could include the fringing cap.

   The BSIM3v3 spice model has a CF parameter which in 0.13um has been set to
zero by at least two large foundries. The open source U. Berkeley 0.13um model
(http://www.eas.asu.edu/~ptm/modelcard/130nm_bulk.txt) has it set to 111aF/um
in the original version, but the latest BSIM4 model has it also set to zero
(http://www.eas.asu.edu/~ptm/modelcard/2006/130nm_bulk.pm).

   A typical poly to substrate fringing cap is 10aF/um.

   I also found a web reference that if CF is missing, its value will be
calculated. So I think I don't have to worry about providing a sideoverlap
value in my tech file. It would require a trick anyway since the nfet/pfet
touches but does not overlap ndif/pdif, so any extracted sideoverlap cap will
always be zero.

   Any comments on these two extraction questions are welcome.

Best regards, Graham Petley