[Magic-dev] Extraction questions for nfet and pfet

[R. Timothy Edwards]

Dear Graham,

> I have seen that the sidewall cap of transistor gate (nfet or pfet) to other
> gate or poly isn't included in the supplied tech files. IMHO there should be
> statements in the extract section like
> 
> sidewall (*poly)/a ~(*poly)/a ~(*poly)/a (*poly)/a         5.0
> sidewall (nmos)/a ~(nmos,*poly)/a ~(nmos,*poly)/a (nmos)/a 5.0
> sidewall (pmos)/a ~(pmos,*poly)/a ~(pmos,*poly)/a (pmos)/a 5.0
> 
> if the poly sidewall cap is 5aF/lambda.

I agree.  However, the first line is in a number of techfiles.  Depending
on the spacing rules for transistor gate-to-gate spacing, the last two
might be considered too small to be of importance, although personally I
think it's more likely just an oversight.

>    I also found a web reference that if CF is missing, its value will be
> calculated. So I think I don't have to worry about providing a sideoverlap
> value in my tech file. It would require a trick anyway since the nfet/pfet
> touches but does not overlap ndif/pdif, so any extracted sideoverlap cap will
> always be zero.

All the techfiles insist that gate-to-diffusion sideoverlap is contained
in the transistor model, so I take their word for it.  On the other hand,
I think your last statement is incorrect---magic looks for "overlap" by
checking an area expanded by 1 unit on all sides (with no condition that
I'm aware of that the overlapping and overlapped types must be on
different planes), which will catch any instance of abutting tiles like
diffusion and transistor gate poly.

					Regards,
					Tim

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