Research Projects

These are the projects that I am currently working on. My interests span many areas within VLSI, QDI design.

Ultra-Low Energy Processing for Ubiquitous Computing

  • Description: The goal of this project is to design a completely self-contained microcontroller, than can perform common tasks of gathering, processing and transmit information using the lowest power envelope at all times.

  • Challenges:

    • Energy efficient computation

    • Zero- power consumption during quiescent state

    • Fast processing for applications such as data processing and location-based services

  • Related Publications:

    • Static Power Reduction techniques for Asynchronous Circuits

    • ULSNAP: An Ultra-low Power Event-Driven Microcontroller for Sensor Network Nodes

  • Collaborators:

    • Rajit Manohar

    • Robert Karmazin

    • Jonathan Tse

    • Benjamin Hill

Secure Chips

  • Description: This project is divided in two main categories:

  • On chip security: Secure circuits and data structures within a chip by using cryptography, physical device properties, and synthesis techniques to harden and secure integrated circuits

  • Trusted fabrication of Integrated Circuits: Preserve confidentiality and integrity of an Integrated Circuits while it is being fabricated by untrusted facilities

  • Challenges:

    • Validation of developed techniques

    • Dataflow of untrusted data

    • Dataflow of corrupt data

  • Related Publications:

    • A Split-Foundry Asynchronous FPGA

  • Collaborators

    • Rajit Manohar

    • Benjamin Hill

    • Robert Karmazin

    • Jonathan Tse

Automated Layout

  • Description: Asynchronous systems take advantage of fast logic families (Domino, DCSVL) to implement arbitrarily function blocks. However, the design time of such blocks is very time consuming since it is mostly done using full-custom layout (aka rectangle pushing). The purpose of these project is to allow fast prototyping of layout using new design paradigms, without loosing the benefits of full-custom layout.

  • Problems:

    • Placement of transistors

    • Global routing problem

    • Local (transistor) routing problem

    • System partitioning and optimization techniques

  • Related Publications:

    • cellTk: Automated Layout for Asynchronous Circuits with Nonstandard Cells

  • Collaborators:

    • Rajit Manohar

    • Robert Karmazin

    • Benjamin Hill

3D-Integration

  • Description: 3D-Integration presents as a solution to alleviate the high-bandwidth requirements of high performance chips comprised of several processing elements connected in an on-chip network. On the other hand, it also has some problems such as inter-die variation within a single chip. We studied the overheads that 3-D impose on the cycle time and thermal density. Our findings show that asynchronous circuits automatically solve the complications that arise with increase variability. We also performed a qualitative study of using TSV as head dissipation pipes.

  • Related Publications:

    • Dynamic electrothermal simulation of three dimensional integrated circuits using standard cell macromodels

    • A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits

    • Variability in 3-D Integrated Circuits

CAD Design

  • Description: CAD tools greatly influence the acceptance of new design paradigms:

    • Manufacturing companies are pressed by tight time-to-market deadlines.

    • Research is usually limited by a

  • The purpose of CAD tools for asynchronous circuits is to allow exploration of the design space and trade-offs of asynchronous circuits while keeping the design manageable by small teams.

  • Challenges:

    • Asynchronous circuits do not "discretize" time

    • Asynchronous circuits do not map directly to standard cell libraries (without loosing performance/energy benefits)

  • So why still asynchronous?

    • Asynchronous is faster by design

    • Provably correct design (Although there are a lot of tools missing for that effect)