Processes contain a set of hidden implicit ports for the power supply nodes. Every process definition effectively declares these supply nodes as the first two ports, !Vdd and !GND, the primary supplies. (The top-level module definition is treated as a process for this purpose, and thus also contains these nodes.) These ports have slightly different connection semantics than ordinary referenceable objects. First, these ports are specially named so that they cannot be accidentally referenced directly; ‘foo.!Vdd’ is syntactically illegal. Second, these ports do not belong into the same set of explicit ports that the user defines; they are not counted in the number of standard ports, for the purpose of writing port connections.
Left unspecified, the default semantics is to automatically connect these supply ports to the respective supply ports belonging to the parent process. Production rules, alike, also connect to these supply ports by default. See PRS Supply Overrides. This behavior is intended for subcircuits that fall under a single supply domain.
To override the supply ports, one writes:
This effectively connects ‘proc.!Vdd’ to Vdd-node, and ‘proc.!GND’ to GND-node. Unlike normal aliases, these connections can be replaced; subsequent supply override statements will break former connections to form new ones.
proc $(myVdd1);
proc $(myVdd2);
results in only ‘proc.!Vdd = myVdd2’, while ‘myVdd1’ remains disconnected from both.
Normal port connections may follow supply overrides, for example, ‘proc_inst $(myVdd, myGND) (x, y, z);’.