True pass-gate logic was missing from the original CAST-PRS implementation. A pass-gate could be emulated as a latch if the `direction' of operation was known at compile time. Not having to support pass-gates greatly simplified other pieces of the tool-chain, such as LVS and PRSIM.
We propose the following syntax for pass-gates:
node_1...3 are production rule literals. In case 1, when node_2 is logic-1, the nodes on either side are connected. In case 2, when node_2 is logic-0, the other terminals are connected. node_2 may be given an optional size to specify the width of the transmission-gate. In all cases, if nodes on opposite sides are both driving in opposite directions, then it is considered a short-circuit (error). If neither side is driving, and the nodes' states are in opposition, then both nodes will become unknown (X). Otherwise, the one side that is being driven will flip the other side.
node_2 may be given an optional <size> argument for specifying gate width.
Technically, one may use pass-gate to construct arbitrary transistor topologies.
Writing a production rule in terms of equivalent pass-gates will not produce sane digital behavior in simulation because of the unidirectional nature of the generated equivalent rule. (They should, however, result in the same netlist in backends.) Hence, all standard logic should be writte as rules, not pass-gates.