Next: VPI Example, Previous: VPI Basics, Up: Co-simulation
We provide a few commands to help debugging connectivity and communication between prsim and the host Verilog simulator.
When this is called before any $to_prsim/$from_prsim connections are made, each connection will be verbosely confirmed in the output.
If arg is 1 (or non-zero), then every value that is transported between verilog and prsim will be verbosely reported.