BitSNAP: Dynamic Significance Compression for a Low Power Sensor Network Asynchronous Processor

Virantha Ekanayake, Clinton Kelly IV, and Rajit Manohar

We present a novel asynchronous processor architecture called BitSNAP that utilizes bit-serial datapaths with dynamic significance compression to yield extremely low-energy consumption. Based on the Sensor Network Asynchronous Processor (SNAP) ISA, BitSNAP can reduce datapath energy consumption by 50% over a comparable parallel-word processor, while still providing performance suited for powering low-energy sensor network nodes. In 180nm CMOS, the processor is expected to run at between 6 and 54 MIPS while consuming 152pJ/ins at 1.8V and just 17pJ/ins at 0.6V.
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