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Song Peng and Rajit Manohar
This paper presents an efficient concurrent failure detection method
for pipelined asynchronous circuits. We first validate permanent and
transient fault modeling in clockless systems. By augmenting the rails
to each data channel and adding extra logic to each circuit module, we
make pipelined asynchronous circuits achieve fail-stop with respect to
hard or soft errors. The experimental evaluations show this method
incurs both reasonable hardware cost and low performance overhead.
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