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John Teifel, David Fang, David Biermann, Clinton Kelly, IV, and Rajit Manohar
We discuss the design of energy-efficient pipelines for asynchronous
VLSI architectures. To maximize throughput in asynchronous pipelines
it is often necessary to insert buffer stages, increasing the energy
overhead.
Instead of optimizing pipelines for minimum energy or maximum
throughput, we consider a joint energy-time metric of the form
Eta, where E is the energy per operation and t is
the time per operation.
We show that pipelines optimized for the Eta energy-time
metric may need fewer buffer stages and we give bounds when such stages can
be removed.
We present several common asynchronous pipeline structures and their
energy-time optimized solutions.
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