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Basit Riaz Sheikh and Rajit Manohar
We present the design and implementation of an asynchronous
high-performance IEEE 754 compliant double-precision floating-point
adder (FPA). We provide a detailed breakdown of the power consumption
of the FPA datapath, and use it to motivate a number of different
data-dependent optimizations for energy-efficiency. Our baseline asynchronous
FPA has a throughput of
2.15 GHz while consuming 69.3 pJ per operation in a 65nm bulk
process. For the same set of nonzero operands, our optimizations
improve the FPA's energy-efficiency to 30.2 pJ per operation while
preserving average throughput, a 56.7% reduction in energy relative
to the baseline design. To our knowledge, this is the first detailed design of a
high-performance asynchronous double-precision floating-point adder.
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