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John Teifel and Rajit Manohar
We discuss high-performance programmable asynchronous pipeline arrays
(PAPAs). These pipeline arrays are coarse-grain field programmable
gate arrays (FPGAs) that realize high data throughput with fine-grain
pipelined asynchronous circuits. We show how the PAPA architecture
maintains most of the speed and energy benefits of a custom
asynchronous design, while also providing post-fabrication logic
reconfigurability. We report results for a prototype PAPA design
in a 0.25um CMOS process that has a peak pipeline throughput of
395MHz for asynchronous logic.
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