A High-Performance Asynchronous FPGA: Test Results

David Fang, John Teifel, and Rajit Manohar

We report test results from a prototype asynchronous FPGA (AFPGA) implemented in TSMC's 0.18um CMOS process. The AFPGA uses SRAM-based configuration bits with pipelined logic blocks and switch boxes. Test results demonstrate a throughput of 674 MHz at 1.8V.
cornell logo