A High-Performance Asynchronous FPGA: Test ResultsDavid Fang, John Teifel, and Rajit ManoharWe report test results from a prototype asynchronous FPGA (AFPGA) implemented in TSMC's 0.18um CMOS process. The AFPGA uses SRAM-based configuration bits with pipelined logic blocks and switch boxes. Test results demonstrate a throughput of 674 MHz at 1.8V. |
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