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Saber Moradi, Nabil Imam, Rajit Manohar, and Giacomo Indiveri
Progress in VLSI technologies are enabling the integration
of large numbers of spiking neural network processing
modules into compact systems. Asynchronous routing circuits
are typically employed to efficiently interface these modules,
and configurable memory is usually used to implement synaptic
connectivity among them. However, supporting arbitrary
network connectivity with conventional routing methods would
require prohibitively large memory resources. We propose a two
stage routing scheme which minimizes the memory requirements
needed to implement scalable and reconfigurable spiking neural
networks with bounded connectivity. Our routing methodology
trades off network configuration flexibility for routing memory
demands and is optimized for the most common and anatomically
realistic neural network topologies. We describe and analyze our
routing method and present a case study with a large neural
network.
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