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Benjamin Tang, Sunil Bhave, Rajit Manohar
CMOS technology scaling has reached a point where the circuit's static
power is as high as the dynamic power. While further process scaling
will only worsen leakage in transistors, it will benefit NEM relay
technology. As asynchronous circuit design helps with dynamic power and
NEM delays with static power, the use of NEM relays in asynchronous VLSI
is ideal for low-power applications. In this paper, we present ways of combining both asynchronous and NEMS technologies and compare them with their
CMOS counterpart. NEM relays can effectively implement not only QDI designs,
but also bundled-data and power-gated circuits. We show in simulation
that a 64-bit C-element, 32-bit PCHB AND, and 8-bit PCHB adder
implemented with NEM relays can achieve over 16X, 25X and 1.7X better
energy-efficiency respectively compared to CMOS in a 90nm technology.
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