Robert Karmazin, Stephen Longfield, Carlos Tadeo Ortega Otero, and Rajit Manohar
Asynchronous circuits offer promise in handling current and future technology
scaling challenges. Unfortunately, their impact has been limited by the
lack of CAD support. We present A-NTUPLACE, a timing-driven placer uniquely
suited to handling quasi delay-insensitive circuits. Our tool uses a
generalization of repetitive event rule systems to identify critical signal
transitions. The cell placement engine, based on the leading academic placer
NTUPlace3, incorporates net weights to minimize critical wirelengths as well
as a novel balancing scheme to ensure isochronic fork constraints are met.
We show that our placer is effective at both prioritizing selected nets as well balancing forks, demonstrating improvements in 3 of our 4 benchmarks.