An Ultra Low Power Processor for Sensor Networks

Virantha Ekanayake, Clinton Kelly IV, and Rajit Manohar

We present a novel processor architecture designed specifically to be used in low-power wireless sensor network nodes. Our sensor network asynchronous processor (SNAP/LE) is based on an asynchronous data-driven 16-bit RISC core with an extremely low-power idle state, and a wakeup response latency on the order of tens of nanoseconds. The processor instruction set is optimized for sensor-network applications, with support for event scheduling, pseudo-random number generation, bitfield operations, and radio/sensor interfaces. A hardware event queue and event coprocessors allow SNAP/LE to avoid the overhead of operating system software such as task schedulers and external interrupt servicing, while still providing a straightforward programming interface to the designer. The processor can meet performance levels required for data monitoring applications while executing instructions with tens of picojoules of energy.

We evaluate the energy consumption of SNAP/LE with several applications representative of the workload found in data-gathering wireless sensor networks. We compare the architecture and software against existing platforms for sensor networks, quantifying both the software and hardware benefits of our approach.

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