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From: R. Timothy Edwards (tim AT stravinsky DOT jhuapl.edu)
Date: Thu Jan 03 2002 - 12:22:53 EST

  • Next message: Jeff W. Sondeen: "Re: process scaling" 

    Dear Jeff,

>> any scaling.  I know that MOSIS rounds off, such as the TSMC 0.25 um
>> process becomes a 0.24 um process in the CIF output sent to MOSIS, and
>> I presume that MOSIS scales it by a factor of 25/24 before passing it

> nope. i don't know where you're getting these .25/.24 numbers.  i
> think mosis does nothing special with layout given in vendor rules.

Sorry, that's my mistake.  Looking closer at the actual TSMC design rules,
I see that their so-called ".25 micron process" is actually a 0.24 micron
process, according to their polysilicon minimum width rule, so the CIF
output from magic (with cifoutput scale = 024) is correct according to
vendor specs.  So why doesn't TSMC call it a 0.24 micron process?  In
this case, does the vendor actually read rules drawn to 0.24 and scale
them to 0.25 themselves?  If so, does that indicate some concern over
specifying design rules at sub-centimicron measurements?

While my comment doesn't apply to the TSMC process, it does apply to the
foundry process I'm currently looking at, the Chartered (Singapore) 0.13
micron process, which does in fact call for design rules on 0.005 micron
boundaries.

After cogitating about it for a while, I decided that it is not necessary
to extend the syntax of the magic tech file, only to relax the conditions
that the cif scale must be integer (GDS) or an even integer (CIF).  Magic
can figure out itself what expander (and reducer, for that matter) values
are needed.  So  "scalefactor 6.5" should suffice for a 0.13 micron
process.

Thanks for your helpful comments.
						Regards,
						Tim

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