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Hi,

So far as what I can understans is there are two ways for vlsi design. Is'nt it?

i) you got verilog code and give it to logic synthesis tools (like Xilinx) which give you the gatelevel netlist of your verilog code and then you connect your FPGA board to usb port and the xilinx will load that gatelevel netlist to FPGA and you can test it and can use it for different applications just as like a chip.

ii) Now the second way is to got verilog code and give it to logic synthesis tools  which give you the gatelevel netlist of your verilog code then use the lay out design of netlist (using magic) and then fabricate your layout design into a chip and use it for applications.

I can't understand if the first technique i.e FPGA is very simple and easy to adopt, then why to bother the complex 2nd technique i.e of layout design and fab? I mean what power lies in using  layout flow which you cannot get from FPGA flow?

(may be I'm wrong somewhere in describing the above two flows but its my understanding, please correct me if so).

Regards

Atif



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