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Tim,
I am not expert on the internals of SPICE, but here are my thoughts on the
subject:

There should not be any difference if the area and perimeter are lumped or
distributed for computing operating points.  operating points are DC
calculations
and the capacitance should have no bearing.

In terms of AC calculations, I would hope that is also does not have any
difference
as long as the total area and total perimeters are correct.  If we remember
back to 
circuits 101, when you build up circuit matrixes, you just lump all parallel
elements 
together anyway.  I can't imagine that SPICE does anything different.

If the above is true, it may be best to keep it lumped because it may lower
the time it
takes to build up a matrix.  For large circuits, this step alone can take
10s of minutes.
I have one sim that takes almost an hour to set up.

I have a copy of the original Nagel tech report on SPICE somewhere in my
office which
may spell it all out.

Mark

 

> -----Original Message-----
> From: R. Timothy Edwards [mailto:tim AT stravinsky DOT jhuapl.edu]
> Sent: Wednesday, April 16, 2003 10:45 AM
> To: agarwala AT ECECS DOT UC.EDU
> Cc: magic-dev AT csl DOT cornell.edu
> Subject: Re: ext2spice
> 
> 
> Dear Anuradha,
> 
> >   I had a question about the spice file that is obtained 
> after layout
> > and extraction using ext2spice. For MOSFETs in addition to 
> the width and
> > length, the drain area(AD), source area(AS), drain perimeter(PD) and
> > source perimeter(PS) is also extracted. From what I gather, 
> these areas
> > and perimeters are used by spice to calculate the 
> capacitances in the
> > small
> > signal model and thus in determing the operating point.
> > 
> > EXT2SPICE also extracts parasitic capcaitances between each node and
> > substrate, and between each pair of nodes. Thus for a mosfet, a
> > capacitance is extracted between each of its three nodes. 
> Do you think
> > that we should extract either the areas and perimeters for 
> each mosfet
> > or the parasitics
> > capacitances between the MOSFET nodes and not both. I was wondering
> > whether extracting both would mislead the simulator and 
> give erroneous
> > simulation results.
> > 
> > I also wanted to know how AD, AS, PD and PS are calculated from the
> > layout. I could not find any document on this. Can you 
> please give me
> > some pointers?
> > 
> > Thanks,
> > Anuradha Agarwal
> 
>    Sorry I haven't answered for a while.  I'm not ignoring your email,
> but I have been trying to find out exactly what SPICE does and doesn't
> do with parasitics, and whether magic's output really does the right
> thing to produce a SPICE deck without redundant entries for node
> capacitances.  I haven't come to any conclusion yet.  So I'm going to
> do what I should have done in the first place, and CC this to the
> magic-dev mailing list, and see if anybody really knows the answer to
> this question.
> 
>    I *can* answer your last question, which is that AD, AS, PD, and
> PS are calculated by doing a tile search on each node and everything
> electrically connected to the node.  A separate answer is output for
> each "resistclass" (as enumerated in the tech file "extract"
> section with each "resist" line.  See the man page for "ext" for
> an explanation of the format of each "node" line.
> 
>    An additional issue is that the extract section of the tech file
> can specify a gate area and perimeter capacitance in each "fet"
> record.  The techfile manual says that these should be left zero.
> I think magic ignores these values in "ext2spice" output whether
> or not they are there.
> 
>    As a side issue, the original standalone programs "ext2spice"
> and "ext2sim" actually hard-coded the resistclass numbers, potentially
> making the extract output invalid for every technology file except
> scmos.  But, the hard-coded resistclasses were not changed after
> some long-ago update to the scmos techfile, so the output of that
> was potentially incorrect, too.  The last couple of revisions of
> magic-7.2 (i.e., current revision 36) avoid this problem by taking
> all extract information from the current magic database and only
> using the information in the .ext file header to confirm that the
> tech file and extract style match.
> 
>    Another addition to version 7.2 is a new keyword "device" for
> the techfile extract section.  "device mosfet ..." works better
> than the equivalent "fet" line, especially for extracting actual
> transistor gate length and width.
> 
>    I pose this question to anyone who knows the answer:  Is there
> any difference to the SPICE simulation between choosing the default
> ext2spice method of piling all area and perimeter values for a node
> on a single transistor connected to that node, and the alternate
> method ("-d" switch, UNDOCUMENTED ??) which distributes the total
> area and perimeter evenly between all transistors connected to the
> node?  Does anybody besides me even know that the "-d" switch
> exists?
> 
> 					Regards,
> 					Tim
> 

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