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From: Rajit Manohar (rajit AT csl DOT cornell.edu)
Date: Fri May 02 2003 - 15:12:24 EDT

  • Next message: cfk: "Re: EDIF"

    >> Have you looked at Xcircuit?
    
    Yes. The difference is that this is a text-based language with support
    for type checking so that you can't accidentally connect incompatible
    signals. It has some nice features for creating complicated
    structures.
    
    >> description language compare to that and to verilog?  (I am imagining it
    >> is at least translatable to verilog RTL...am I close?)
    
    It's designed for asynchronous circuits, so some of the constructs
    could be easily translated to verilog, others would be cumbersome.
    The big difference between it and languages like verlog/vhdl, is that
    it is purely a circuit description/"rtl-level" description
    language. So you can't express things that aren't synthesizable. For
    instance, you can't say something like:
    
     x <= #50 y
    
    (i.e. a delayed assignment). This makes the life of a synthesis tool a
    lot easier (IMHO).
    
    >> [jg]Is COSMOS open source?  Must be good if Intel is using it...
    
    It's a compiled simulator with some nice features. Not sure if it is
    open source or not... it probably is. It was written by Randy Bryant's 
    group at CMU.
    
    -Rajit
    


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