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From: R. Timothy Edwards (tim AT stravinsky DOT jhuapl.edu) Date: Mon Sep 15 2003 - 10:36:59 EDT
Dear Atif, The ultimate authority on these questions are the people who run the fab foundries. I assume you're asking about the "why" of rules, in general, not just the scalable CMOS rules. Most rules arise from a couple of factors, namely 1) the precision with which masks can be aligned and 2) the diffusion profile. The best processes are those which are "self aligning"; for example, the poly mask and the diffusion mask can be misaligned, but the resulting transistor will still have the same channel region. Diffusion regions do not have the sharp edges that the layout shows; the "edge" is really a gaussian profile. Wells and diffusion regions exist well beyond the geometric boundaries shown in the layout. The design rules ensure that layers or devices which might be affected by the diffusion profile are far enough away. But the gaussian profile means that while some diffusion exists away from the drawn region, the full dose occurs somewhere within the boundary of the drawn region, and the design rules have to account for that, as well. The actual allowed values (in microns) specified by the foundry design rules depend on 1) the steepness of the gaussian profile of various diffusion and implant types, and 2) the ability of the foundry machinery to align masks. There are other considerations (metal migration, electrostatic discharge, surface smoothness, "bird's beak" formation, etc., etc.) but these are the main two. > i) poly-poly spacing is 2 lambda Generally speaking, width and spacing rules will be about the same. Poly rules are usually defined by the mechanical limits of the fabrication machinery. > ii) 1 lambda of diffusion and metal surrounding cut Alignment: For diffusion, you want to make sure that the contact is completely over the diffusion, to maintain the process spec. for the maximum contact resistance. Likewise for metal (the metal layer *is* the contact, in most cases). > iii) 2 lambda overhang of poly at transistor gate Alignment. If the poly mask shifts too far, you could end up with a short instead of a transistor. > iv) why ndiff to pdiff spacing is so large (10 lambda) Diffusion. Need to keep the pwell diffusion and pdiff diffusion apart. Because well and diffusion are both p-type, getting them too close could cause a short or breakdown under a high potential difference. This distance tends to vary quite a bit from process to process (remember that scmos rules are meant to cover a wide variety of processes and scales). > v) why metal-metal spacing larger than poly-poly spacing I assume that this simply has to do with the different materials and/or methods of fabrication. This is not necessarily true for all processes; I know of several in which if the rules are all rounded up to the nearest lambda, m1-m1 and poly-poly spacing are the same. > vi) why metal2-metal2 spacing larger than metal1-metal1 spaning Not necessarily true for all processes. Usually the rule is that the top-level metal has more conservative rules, and all the other metal layers have the same rules. Top-level metal may have different properties, such as being thicker or using a different material. Regards, Tim
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