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Hi all,

I have released an updated version of my open source standard cell libraries.
This release has increased the number of cells in the vsclib from 69 to 114.
The extra cells are AND, OR and buffer gates. As before, all cells are
documented for a generic 0.13um timing in the on-line data book at

http://www.vlsitechnology.org/html/vsclib_gif_index.html

The release includes layout descriptions in Alliance, Magic and Excel (!)
formats, schematics written by Xcircuit in Postscript, and full
characterisation scripts that run with Winspice3 and generate Synopsys .LIB
format lookup tables. The Alliance design flow is supported with 0.13um and
0.35um timing files, and an example of the flow with the vsclib is included in
the release, available for download at

http://www.vlsitechnology.org/library_2.6.tar.gz

Any comments or feedback are welcome.
Best regards, Graham Petley

=====
Graham Petley
ASIC Specialist and Consulting Engineer
Metzstrasse 14, 81667 Munich, Germany
Phone +49-89-6349-7630   Mobile +49-177-282-5072
http://www.vlsitechnology.org/

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