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Song Peng and Rajit Manohar
This paper presents a systematic design for yield enhancement
of asynchronous logic circuits using 3-D (3-
Dimensional) integration technology. In this design, the target
asynchronous circuits on one planar device layer which
is fabricated with aggressive technology, are built on fault
tolerant graph models with extra spare resources, and can
be reconfigured by autonomous reconfiguration logic on another
planar device layer which is fabricated with conservative
technology, in the presence of hard errors. The yield
analysis shows that this method can result in 20-30% overall
yield enhancement. This method can be conveniently
applied to clocked designs without significant changes.
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