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Magic Mailing List |
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From: Stefanos Sidiropoulos (stefanos AT rambus DOT com) Date: Wed Apr 05 2000 - 13:26:26 EDT
At 08:15 AM 4/5/00 , you wrote: >well, i believe that each metal layer *must* be on it's own plane, so >the issue is contacts to metal. the new techfiles have both >traditional contacts, where each resides on the same plane as the >metal it connects to (eg. layer 'm2c' resides on the metal2 plane), as >well as new (named "generic") contacts and vias (gc, gv1, gv2, etc.), >which do reside on their own plane. the main need for these is to >.... If you have specific reasons for that I would not object at all.. >they now have the 225-type limit needed for SCN6M_*.tech27 > > > 2) There is a bug in the files which they never fixed: nnd connects to > pdiff > > and ppd connects to ndiff. In real silicon this is a zener diode but > > given > > these techfiles magic treats it as a perfect short. > >believe me, since i learned this first hand (read that, chip failure), >the "diode" between ohmic and diffusion *is* a short in all >*silicided* processes; silicide is metal put into the diffusions to >lower the resistance. it does it so well that in some of HP's >standard library cells, there're no actual contacts to ohmics which >abut diffusion (rather the contact to diffusion is enough for both). Interesting... My counter argument would be that you should not be using p+/n+ diodes for anything.. Besides I don't know of any sane person who would want i.e. their clock buffer powered through silicide. If HP does it in their standard cells I am sure they have some way of verifying the IR drop and electromigration problems this creates (otherwise I feel sorry for them). Since however you don't supply any such tool with your tech file you should not leave open such a huge methodology hole.. Regards, -- Stefanos
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