|
|
Magic Mailing List |
|
From: Jeff W. Sondeen (sondeen AT rcf-fs DOT usc.edu) Date: Wed Apr 05 2000 - 16:25:35 EDT
> >believe me, since i learned this first hand (read that, chip failure), > >the "diode" between ohmic and diffusion *is* a short in all > >*silicided* processes; silicide is metal put into the diffusions to > >lower the resistance. it does it so well that in some of HP's > >standard library cells, there're no actual contacts to ohmics which > >abut diffusion (rather the contact to diffusion is enough for both). > > > > Interesting... My counter argument would be that you should not > be using p+/n+ diodes for anything.. Besides I don't know of any > sane person who would want i.e. their clock buffer powered through > silicide. If HP does it in their standard cells I am sure they have > some way of verifying the IR drop and electromigration problems > this creates (otherwise I feel sorry for them). Since however you > don't supply any such tool with your tech file you should not > leave open such a huge methodology hole.. > maybe i've misunderstood you. what i'm talking about is that, if you look at the attached .mag file with a non-silicided process techfile, like SCNA.80.tech27, the wells labelled 'pw' and 'nw' will *not* be connected to gnd and vdd, respectively, since there will be n+/p+ junctions between the transistor diffusions and the ohmic diffusions (well-contacts). however, if you use a silicided process techfile, like SCN3M_SUBM.30.tech27, you will see that the wells are connected to their respective supplies, since the silicide removes those n+/p+ junctions, reflecting the fabricated part. it may be a "weak" connection but it doesn't have to carry much current (hopefully) to keep the wells biased. however, how can i make this clearer, it's NOT weak! magic tech scmos timestamp 954965243 << nwell >> rect 3 24 19 48 << pwell >> rect 3 0 19 24 << ntransistor >> rect 9 12 13 14 << ptransistor >> rect 9 34 13 36 << ndiffusion >> rect 9 14 13 15 rect 9 11 13 12 << pdiffusion >> rect 9 36 13 37 rect 9 33 13 34 << ndcontact >> rect 9 15 13 19 rect 9 7 13 11 << pdcontact >> rect 9 37 13 41 rect 9 29 13 33 << psubstratepdiff >> rect 9 3 13 7 << nsubstratendiff >> rect 9 41 13 45 << polysilicon >> rect 4 34 9 36 rect 13 34 15 36 rect 4 26 6 34 rect 4 14 6 22 rect 4 12 9 14 rect 13 12 15 14 << polycontact >> rect 2 22 6 26 << metal1 >> rect 0 41 19 45 rect 0 37 9 41 rect 13 37 19 41 rect 9 26 13 29 rect 9 22 17 26 rect 9 19 13 22 rect 0 7 9 11 rect 13 7 19 11 rect 0 3 19 7 << labels >> rlabel metal1 6 7 6 7 2 gnd:1 rlabel metal1 6 41 6 41 4 vdd:1 rlabel pwell 17 18 17 18 7 pw rlabel nwell 17 29 17 29 7 nw << end >>
|
|
|
|