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Magic Mailing List |
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From: Andrew Lines (lines AT avlsi DOT com) Date: Sat May 20 2000 - 13:37:12 EDT
As we all know, Magic generates the well and select layers (CWN,CWP,CSN,CSP) by bloating and munging the diffusion and substrate diffusion paints. Although with appropriate DRC rules this can satisfy all the overlap and spacing to incompatible layers, it often generates foundry design rule violations on spacing to like layers or makes narrow bridges between like layers. We have fabbed chips in the past through MOSIS with thousands of such "errors" and they work fine. We asked a foundry (UMC) and they gave us a fairly flimsy sounding explanation that well to well spacing of electrically connected nwells might cause latchup, and that nselect to nselect spacing might increase punchthrough. Does anybody have a good explanation of why these types of errors are or are not a problem? Does anybody using Magic routinely paint all wells and selects to avoid these types of problems with the generated layers?
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