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Andrew Lines writes:
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 > As we all know, Magic generates the well and select layers
 > (CWN,CWP,CSN,CSP) by bloating and munging the diffusion and substrate
 > diffusion paints.  Although with appropriate DRC rules this can satisfy
 > all the overlap and spacing to incompatible layers, it often generates
 > foundry design rule violations on spacing to like layers or makes narrow
 > bridges between like layers.  We have fabbed chips in the past through
 > MOSIS with thousands of such "errors" and they work fine.
 > 
 > We asked a foundry (UMC) and they gave us a fairly flimsy sounding
 > explanation that well to well spacing of electrically connected nwells
 > might cause latchup, and that nselect to nselect spacing might increase
 > punchthrough.  Does anybody have a good explanation of why these types
 > of errors are or are not a problem?  Does anybody using Magic routinely
 > paint all wells and selects to avoid these types of problems with the
 > generated layers?

i believe Mosis bloats and shrinks all Well and Select layers (by 1/2
the spacing) to fill less than minimum spacings (which crop up in
magic when regions are cater-corner), but has never dealt with the
resulting bridges between cater-corner regions (that is, doesn't try
to remove them since that would just reintroduce the spacing
violation). it's not clear what a 6x1 lambda Nwell bridge region in
the photoresist produces in practice -- perhaps the photoresist hole
is never opened since the processing assumed a larger minimum hole
size.

we routinely draw wells (so don't have well bridges) but certainly
have fabbed 1000's of select bridges throught the years. i also
haven't heard of any problem related to them.

/jeff

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 > tel;fax:(626) 844-2951
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