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in trying to create native (eg tsmc design rule) techfiles, smaller
pitch overhead can be achieved if "shrinks" per layer on cif/strm out
were possible.  the trouble is that these would disconnect shapes that
abut across cells (as each cell would shrink it's shape and so a gap
of 2*shrink would be formed between them).  it could be avoided if
there were a 'must_overlap' (similar to the 'no_overlap') drc rule.
then layers that were going to be shrunk on cif/gds out could specify
that they need an overlap >= 2*shrink, so they would still connect
after cif/gds output.

is there an easier way to get this effect ?

thanks,
/jeff

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