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From: Erwin Prinz (rzfm20) (rzfm20 AT email DOT sps.mot.com)
Date: Thu Nov 01 2001 - 13:28:58 EST

  • Next message: Prakash: "RE: MAGIC DRC question" 

    All:

There was a question about what to do about intentional design rule
violations. We don't let designs go to the mask shop if they have any.
The issue is that for large system on a chip designs it is easy to miss
other issues when introducing intentional violations. So, for example
for a floating gate F/N oxide which requires an extra mask to fabricate
anyway (to etch off the high voltage gate oxide before growing the F/N
oxide) it is better to either add a plane to the technology file for
"oxide" with types "low voltage oxide", "high voltage oxide", and
"tunnel oxide") or to add a tile to form a special channel with tunnel
oxide underneath. This would look as follows, where I have elected to
define a plane rather than defining a new tile, mainly because I use
"magic" to build device engineering test structures where I need
complete control over the various masks used for processing.

planes
 well,w

# this is the gate oxide plane - it can include low voltage, high
voltage, medium voltage gate oxides, and ONO interpoly dielectric
 gate, g
 implant,i
 active,a
 metal1,m1
 metal2,m2
 metal3,m3
 metal4,m4
 passivation,p
 contact
 via1
 via2
 via3
end

types
 ...
 /* oxide areas - used to distinguish active areas */

 gate  tunnel_oxide
 gate  hvarea,hvgateoxide,hvoxide,hvgate,hvox,hvo,hv
 gate  ono,onoarea
 gate  dgo
...
end

Of course, we then have complete design rules for all devices including
the tunnel oxide device.

Best regards,

Erwin Prinz (ejprinz AT austin DOT rr.com)

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